LIVE WEBINAR: Accelerating Verification Component development with OSVVM Model Independent Transactions

OSVVM is a competitive solution with SystemVerilog + UVM for FPGA Verification. World-wide, 18% of the FPGA market uses OSVVM [1] – or alternately 36% of the VHDL FPGA market uses OSVVM. In Europe, in the FPGA market, OSVVM (with 36%) leads SystemVerilog+UVM (with 26%).    

OSVVM is an innovator and leader in the development of VHDL Verification Methodology. Our approach has been evolving in SynthWorks classes since 1997 and started being released as open source in 2011. So how does it compare to SystemVerilog?

  • Constrained Random – Supported via RandomPkg and coding styles – an OSVVM innovation
  • Functional Coverage – Supported via CoveragePkg – an OSVVM innovation
  • Scoreboards – Supported via ScoreboardGenericPkg – an OSVVM innovation
  • Error reporting and Messaging – supported via AlertLogPkg – concepts borrowed from numerous sources
  • Transaction based testbenches and verification components – in our classes since 1997
  • Memory Modeling – data structure for efficient creation of memories through sparse allocation.
  • Process Synchronization – barrier synchronization (an OSVVM innovation) as well as other methods.

Is OSVVM supported by my simulator? Currently OSVVM is supported by simulators from Mentor, Aldec, Cadence, Synopsys, and GHDL. This is great support and our goal is to keep it this way. When we upgrade existing features in the library, we test to make sure we do not break support within our community. OTOH, when we introduce new capability (generally in separate packages) and there is a significant advantage to using advanced VHDL constructs – such as it simplifies how the item is used, then it is likely we will use it – as a result, some of OSVVM's Verification IP uses records with unconstrained arrays. We also strictly avoid using deprecated language features - such as shared variables that have an ordinary type.

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