Cadence Genus Synthesis Solution Enables Fuji Xerox to Improve Multi-Functional Printer SoCs Design Development

Fuji Xerox reduces design iteration time more than 50 percent and achieves up to 16 percent area reduction

SAN JOSE, Calif., Oct. 2, 2017 — (PRNewswire) —  Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that Fuji Xerox Co., Ltd. used the Cadence® Genus Synthesis Solution to improve the development of its multi-functional printer SoCs. The Cadence solution enabled Fuji Xerox to reduce its timing closure schedule more than 50 percent and achieve up to 16 percent area reduction for its sub-blocks, resulting in an eight percent total chip area reduction when compared with its previous solution.

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For more information on the Genus Synthesis Solution, please visit www.cadence.com/go/genus.

Fuji Xerox employed the Genus Synthesis Solution's innovative early physical flow, which rapidly models physical effects such as placement and routing from the earliest stages of logic synthesis. This capability helped them minimize gate area of SoC while also meeting performance targets, which led to improved power, performance and area (PPA) and faster time to market. Additionally, the Cadence solution's accurate physical effect modeling improved performance correlation to place and route, which allowed Fuji-Xerox design engineers to close the design more easily, reduce the turnaround time (TAT) iterations with their ASIC vendor and shorten the overall development schedule.

"Our customers are requesting that we support more value-added features for multi-functional printers, which means that SoC development has become more and more complex," said Noriaki Tsuchiya, ASIC Design Group Manager, Controller Platform Development 1, Software Development Group, Fuji Xerox Co., Ltd. "The Genus Synthesis Solution's area and timing optimization engines addressed our design quality and TAT requirements, and we've saved on our SoC design engineering resources. Given our successes with the Cadence solution, we plan to continue using it and evaluate the Genus physical optimization flow to further optimize PPA with our next-generation SoC designs."

The Genus Synthesis Solution is a next-generation RTL synthesis and physical synthesis engine that addresses the productivity challenges faced by SoC designers. It is a part of the Cadence digital design platform that supports the company's overall System Design Enablement strategy, which enables system and semiconductor companies to create complete, differentiated end products more efficiently.

About Cadence
Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence software, hardware and semiconductor IP are used by customers to deliver products to market faster. The company's System Design Enablement strategy helps customers develop differentiated products—from chips to boards to systems—in mobile, consumer, cloud datacenter, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For. Learn more at cadence.com.

© 2017 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.

For more information, please contact:
Cadence Newsroom
408-944-7039
newsroom@cadence.com

 

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SOURCE Cadence Design Systems, Inc.

Contact:
Cadence Design Systems, Inc.
Web: http://www.cadence.com




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