LOWELL, MA -- (Marketwired) -- May 21, 2015 -- Agnisys, Inc. announces immediate availability of ARV™ - Automatic Register Verification , an add-on product to IDesignSpec™, that enhances an already powerful register specification solution with capability to automate the register verification process for SoCs, IP and FPGA semiconductor projects. ARV saves semiconductor teams time and improves quality by enabling complete code coverage for design registers that are the key integration point for semiconductor design, IP, software and interfaces.
ARV comes in two configurations: ARV-Formal™ and ARV-Sim™.
ARV-Formal is a complete solution that takes the register specification and RTL design as input and performs a formal proof to ensure all register operations conform to the specification. ARV-Formal is powered by 360-DV LaunchPad™, an adaptive formal technology platform from OneSpin Solutions that allows third-party companies with limited knowledge of formal technology to develop and deliver formal-based apps. It provides an automated, integrated flow that leverages the exhaustive nature of modern formal verification technology. ARV-Formal automatically generates assertions directly from the specification and executes them using the integrated formal engine, therefore completely automating setup and ensuring a very rapid return on investment. The formal engine is included as part of ARV-Formal, eliminating the need for an external formal product.
ARV-Sim is a complete register verification solution that integrates with Synopsys VCS®, Cadence Incisive® and Mentor Questa® simulators. ARV-Sim completely automates the UVM verification process. This approach eliminates the lengthy and error prone UVM test bench and sequence creation process. ARV-Sim provides the positive and negative sequences automatically -- the actual test sequences that stimulate the hardware to ensure that the implementation is correct. ARV-Sim not only tests the register implementation but also the interface between the registers and the application logic.
The Register Verification Challenge
Register verification is a significant part of the design verification problem. It is one of the first aspects of the design that must be tested because the rest of the semiconductor functionality depends on the accuracy of the register implementation. That is because registers contain the configuration setting of the hardware and is the basis of the hardware / software interface.
ARV Ensures the Register Implementation is Correct:
- ARV-Sim ensures that the coverage metrics are achieved. The only way to know you have tested all scenarios is by the coverage. ARV provides the coverage metrics and writes tests to enable 100% coverage on the registers.
- ARV-Sim supports testing of special registers, for example, lock registers, shadow registers, register aliases, interrupts etc. It generates sequences for these special registers.
- ARV-Sim ensures that the application logic correctly interfaces with the registers and memories.
- Automatically creates register-focused coverage reports.
- User can check either the IDesignSpec generated RTL code, the user's own implementation, or a mix of the two with standard buses or user defined buses and transactions.
- Being an add-on to IDesignSpec, users can import IP-XACT, SystemRDL, RALF, Word, Excel, CSV, XML and host of other formats.
Agnisys at Design Automation Conference
Agnisys will demonstrate ARV-Formal and ARV-Sim and its entire register management and verification products at the 52nd Design Automation Conference (DAC) in Booth #2509 June 8-10 at the Moscone Center in San Francisco.
Agnisys, Inc. is focused on providing System Verilog and Universal Verification Methodology Products, Services and Training to Design Verification engineers. Agnisys enables semiconductor companies to increase productivity and proficiency while eliminating the design and verification errors in advanced System-on-Chip (SoC), Field Programmable Gate Array (FPGA) and Intellectual Property (IP) semiconductor designs.
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