HDL Design House Announces MIPI DSI (Controller + D-PHY) IP Solutions

Belgrade, Serbia -- November 26th, 2012 -- HDL Design House, provider of high performance digital and analog IP cores and SoC design and verification services, has announced availability of MIPI DSI Host (HIP 3500) and Peripheral (HIP 3510) IP cores, fully compliant with the MIPI Alliance DSI specification, as part of HDL Design House FlexIP core library. These DSI IP solutions can be used in tandem with HDL Design House MIPI D-PHY IP core, available in advanced technology nodes and with silicon proven status. HDL Design House has been a MIPI Alliance Contributor Member since 2010.

HDL Design House MIPI DSI Host IP core (HIP 3500) is a configurable digital core, compliant with the MIPI Alliance DSI specification, providing a high-speed serial interface between an application processor and MIPI DSI compliant display. It supports MIPI DSI protocol version 1.1, MIPI DCS version 1.0, MIPI DBI version 2.0, MIPI DPI version 2.0, MIPI D-PHY version 1.0. The HIP 3500 is fully compliant with AMBA AHB Version 2.0 Compliant Slave Interface. HDL Design House HIP 3500 can be configured to handle 1 to 4 data lanes and supports image resolutions: QQVGA, QVGA, VGA, WVGA, XVGA, Full-HD and pixel formats: RGB 16, 18, 24 bits (a.k.a. RGB565, RGB666, RGB888).

HDL Design House MIPI DSI Periph (Device) IP core (HIP 3510) receives pixel data and commands from host processor through D-PHY interface and sends data to DPI or DBI interfaces. HIP 3510 is a highly configurable digital IP core, supporting 1 to 4 data lanes. The HIP 3510 is fully compliant to MIPI Alliance's DSI, MIPI DBI version 2.0, DPI version 2.0, and DCS standards, as well as to AMBA's AHB specification. HDL Design House HIP 3500 can be configured to handle 1 to 4 data lanes and supports image resolutions: QQVGA, QVGA, VGA, WVGA, XVGA, Full-HD and pixel formats: RGB 16, 18, 24 bits, (a.k.a. RGB565, RGB666, RGB888). It supports both command and video modes of operation.

HDL Design House MIPI DSI solutions are available now, along with the silicon-proven MIPI D-PHY IP core in 65nm and 40nm.

About HDL DH FlexIP core library

The FlexIP core library includes a broad portfolio of high-quality, silicon proven digital and analog IP cores for SoC designs. The library covers a large number of standards and protocols such as HDMI, DisplayPort, MIPI (M-PHY, D-PHY, DSI, UniPro and CSI, DigRF, BIF), USF, I2S, Serial RapidIO, SPI flash memory controller, PCI Express, SATA, USB 3.0, and others. Apart from the large number of supported protocols and standards, one of the greatest competitive advantage for users of the FlexIP core library is HDL Design House outstanding capabilities in providing integration services, customization of the IP core at customer's request, verification solutions for the given IP core, as well as on site support. For more information on the FlexIP core library, please go to http://www.hdl-dh.com/products.html

About HDL Design House

HDL Design House delivers leading-edge digital and analog, design and verification services and products in numerous areas of SoC and complex FPGA designs. The company also develops IP cores and component (VITAL) models for major SoC product developers. Founded in 2001 and currently employing 60 engineers working in two design centers in Serbia, HDL Design House mission is to deliver high quality products and services, with flexible licensing models, competitive pricing and responsible technical support. The company was awarded ISO 9001:2000 and ISO 27001:2005 certifications in December 2006 and has achieved certifications from Direct Assessment Services (DAS). For more information, please visit www.hdl-dh.com

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