| Accellera |
The Accellera Formal Verification Technical Committee has been created to develop and promote a property specification language compatible with Verilog (IEEE-1364) and VHDL (IEEE-1076). Visit: www.accellera.org for further information. |
| ADA |
A programming language. |
| ASCII |
American Standard Code for Information Interchange, the encoding scheme for text files, each character is represented by a 1 byte number. |
| ASIC |
Application Specific Integrated Circuit, a silicon chip custom designed for a specific purpose. |
| Behavior |
A specification of signal values over time. For example, "the signal req is true for three cycles; on the fourth cycle the signal req is still true and the signal ack is false." |
| Behavior coverage |
The percentage of expected behaviors detected by the checker in the dynamic results. This applies to both data coverage and temporal behavior. Behavior coverage is a user-defined metric that typically reflects the contents of the verification plan. The verification engineer defines a set of behaviors that the system must be tested for. For example, if the system can read and write data, to several memory blocks |
| Branch coverage |
Coverage measurement also known as block coverage, it checks each branch in a branching construct such as an 'if' or 'case' statement has been tested. |
| BFMs |
Bus functional models, a piece of software designed to mimic the behavior of a hardware interface device. |
| Coverage analysis |
A technique for measuring how much of the source code of a computer program or hardware description has been executed by a test run or simulation. |
| Control file |
A file which is the cross reference between the coverage analysis results file (history file) and the original HDL source code (Verification Navigator specific). |
| Core |
Also called IP Cores these are hardware descriptions of a piece of reusable hardware, such as a Pentium processor model. These can be incorporated into a larger design. |
| Design rule checker |
A software tool that performs static checks on HDL. |
| DFT |
Design For Test An approach that is used during the design phase of an IC that concentrates on providing a means of testing an integrated circuit after it has been manufactured. |
| DUT |
Design (or Device) Under Test, this is the circuit description which is being tested by simulation. |
| Dynamic check |
A technique of checking a set of properties from a set of simulation results. Note: The fact that the property holds for the set of simulation results is not a proof that the property is true for the system. |
| Dynamic property checking |
A technique that checks that a design does or does not conform to a specified property for a set of stimuli. |
| Dynamic verification |
Exercising a model or models of a design, or a hardware implementation of the design with a set of stimuli. |
| Expected behavior |
A behaviour that should occur in the design. This behavior is reported as "covered" if the dynamic results exhibit it. See also prohibited behavior. |
| Fault Simulation |
This is a simulation technique used to verify the effectiveness of test patterns which will be used to evaluate the manufactured device. Usually the fault model used assumes that each node in the circuit is either shorted to power (stuck-at-1) or ground (stuck-at-0). The fault simulator tests that simulation results are different for a fault free circuit and a circuit with a fault. |
| FEC |
Focused Expression Coverage, a coverage measurement for Boolean expressions which only requires N + 1 test patterns, where N is the number of inputs to the expression, instead of the 2^N maximum number of input combinations. |
| Formal verification |
Use of various types of logic and mathematical methods to verify the correctness of IC logic or system interactions. Equivalence checking is the most common formal verification method, which is used to compare the design that is being created against a design that is already proven accurate. |
| FSM |
Finite State Machine An electronic circuit that has a predictable or finite state that is based on a combination of the circuit's previous state and the circuit's current set of inputs. |
| FSM arc coverage |
A technique for checking that every arc or transition between states within a FSM has been traversed. |
| FSM coverage |
A technique for measuring how much of a FSM has been covered in respect of state-coverage, arc-coverage and path-coverage. |
| FSM cycle |
A cycle is a directed set of states that returns to its starting state without passing through any state more than one. |
| FSM link |
A directed set of states that does not repeat. An example would be an initialization sequence. |
| FSM path coverage |
Visited state and arc coverage do not necessarily measure the extent to which the functionality of a FSM has been verified. The more powerful path coverage metric measures that all the paths or routes through a sequence of visited states or arcs in the FSM have actually been taken. |
| FSM state coverage |
A technique for checking that every state of a FSM has been visited. Often referred to as "visited state coverage." |
| FSM supercycle |
A longer cycle (than an FSM cycle) that identifies the high level functionality and provides a concise summary of the overall structure of the FSM. |
| Gate level |
The point in the design process where the circuit is completely described as an interconnection of logic gates, such as NAND, NOR and D-type registers. |
| Graphical editors |
A software tool that enables the architecture and definition of a design to be captured graphically. |
| HDL |
Hardware Description Language, a programming language like way of describing hardware. The two most common HDL's are Verilog and VHDL. |
| Instrument |
To instrument an HDL circuit description is the process of adding extra HDL code to determine what has been executed during the simulation. |
| IP |
Intellectual Property or IP Cores these are hardware descriptions of a piece of reusable hardware, such as a Pentium processor model. These can be incorporated into a larger design. |
| JTAG |
Joint Test Access Group A consortium of individuals from North American companies whose objective is to tackle the challenges of testing high density IC devices. |
| Linters |
A software tool that performs a predefined set of fixed checks on a coding language such as Verilog, VHDL, C or C++. |
| Logic synthesis |
The process of converting a RTL (Register Transfer Level) hardware description to gate level, this is usually automated by software tools. |
| Model checking |
A formal verification technique that compares the implementation of a design to a set of user-specified properties. Determines whether a set of properties hold true for the given implementation of a design. If the property is false, a counter-example is produced. Also referred to as property checking. |
| Netlist |
A circuit description which consists of a list of interconnected sub-blocks, they can be written in Verilog, VHDL or a variety of standard and proprietary netlist languages. |
| OpenMORE |
Open Measure Of Reuse Excellence. A design scoring system devised by Mentor and Synopsys.
Visit www.openmore.com for full details. |
| Pascal |
A programming language. |
| Path coverage |
A coverage measurement which checks that all the paths through consecutive branching constructs in procedural blocks are tested. |
| Perl |
A programming language. |
| Post-simulation results filtering |
A technique that allows the elimination of coverage analysis errors that are associated with unreachable or unexecutable HDL |
| Probe |
A software `monitor' point which is included in an HDL description for the purpose of collecting coverage analysis information. |
| Prohibited behavior |
A behavior that should not occur in the design. A violation of prohibited behavior is reported if the dynamic results exhibit the behaviour. |
| Property |
A statement that a given behavior is "expected" or "prohibited." |
| Property coverage |
Property checking supported by behavior coverage. This is the association between a property and the scenarios in which the property should be checked. Scenarios are described by means of expected behaviors. |
| Property checking |
A formal verification technique that verifies that a design does or does not conform to a specified property under all possible sets of legal input conditions. Like HDL rule checking, the design is checked for conformance with one or more properties producing errors called violations where the design does not conform to the property. |
| RMM |
Reuse Methodology Manual A set of guidelines that define good coding styles for HDL design. See Appendix A for more details. |
| RTL |
Register Transfer Level, the point where the design is written as a register transfer description. A register transfer description is a type of a behavioral description which is closely related to the hardware implementation. The description is written in terms of register banks and combinational logic. |
| Rule-based checkers |
A software tool that performs static checks on HDL by applying a set of rules (defined by one or more rule-databases) that have been selected and customised by the user. |
| State diagram |
Graphical method of showing the pictorial representation of a structure and interaction within a finite state machine. |
| SoC |
System on a Chip. The term used to describe the large scale integration of a complete system onto a single piece of silicon. |
| Statement coverage |
Also known as line coverage, this is a coverage analysis metric which checks the number of executable statement that have actually been executed in the HDL description being tested. |
| Synthesis |
See logic synthesis. |
| Tabular trace |
A method of recording the results from a simulation run in a compact tabular or column orientated format. Information is only recorded when a change occurs on a traced signal. Often referred to as a trace file or tab file. |
| TAP controller |
Test Access Port controller A design that is often used as a benchmark within the EDA industry for checking the performance of FSM coverage analysis tools. A TAP controller is a state machine (with 16 possible states) that is used to control operations associated with the boundary scan cells (that appear on the periphery) of an integrated circuit. |
| Test bench |
A set of stimuli (plus response checking) that is used to check the correct operation of a circuit description. |
| Test suite analysis |
A technique for sorting the test benches, used in the regression suite, in the most productive order so that the test bench that gives the maximum amount of coverage in the minimum amount of simulation time is ranked the highest in the list. The process is repeated on an iterative basis until all the test benches have been analyzed. Non-productive test benches are not included in the final list. |
| Test suite optimization |
See test suite analysis. |
| Text editors |
A software tool that enables text files to be created and modified. |
| Toggle coverage |
A coverage measurement which checks that each bit of a signal has switched between logic-0 and logic-1 (or vice versa) and back again. |
| Verilog |
A hardware description language. |
| VHDL |
VHSIC Hardware Description Language. |
| VHSIC |
Very High Speed Integrated Circuit. |
