Please Join Us at DAC to Catch Up on Breker’s Technology

The Design Automation Conference (DAC) us nearly upon us once again, this year returning to Austin in just a few days. The first-ever DAC in Austin was held three years ago and it was by all accounts a really good show. It was nice seeing new faces who could carve out an afternoon to visit the exhibit floor but who couldn’t get permission to travel when DAC is elsewhere. We were very pleased by both the number of people who stopped by our booth and their level of interest in what we do.

As you may know, Breker was born in Austin and so it will be a bit of a homecoming for us to return again. Austin features many fun activities, especially musical in nature, and great BBQ restaurants. We’ll be glad to provide suggestions and pointers for these if you ask, but for today’s post we’d like to fill you in what we will be doing at the show this year. We welcome any comments or questions that you may have.

When the DAC program was first announced in late March, we posted a summary of the show and listed some of the sessions that we thought might be of particular interest to you, our loyal readers of The Breker Trekker. Of course, DAC is an event with both a world-class technical conference and the largest annual exhibition from vendors of EDA tools, IP, semiconductors, systems, and services. Will Breker be there? We wouldn’t miss it for the world!

As always, our booth will have multiple demo stations where you can connect directly with our technical staff, watch our products in action, and dig as deep as you’d like. If you prefer a private meeting to discuss the details of how we can help verify your most complex chips, we invite you to schedule a session in our suite. New for this year is an intermediate space, a seating cluster where you can sit and talk with us while we all rest our tired feet.

We have recently added several new features to our Trek family of products, and you will be able to see these demonstrated in our booth at DAC:

• A new memory map viewer showing all bytes allocated, used, and modified by our test cases, an essential tool for debugging design errors that we uncover
• New performance monitor features to show how well our highly complex test cases are exercising key aspects of your design’s architecture
• New integration with Synopsys VC Verification IP (VIP) and Verdi Protocol Analyzer to show how well our test cases are exercising your standard interfaces
• Deeper integration with Verdi Coverage from Synopsys for a single view of verification progress, merging our novel system-level coverage with all traditional metrics

You may have noticed that we issued three press releases last week leading up to DAC. In addition to the expanded integration with the Synopsys verification products, we announced partnerships with Semifore and Agnisys to create flows from their tools to ours. We’ll be glad to answer questions about any of this integration work or whatever else you’d like to know. You can find us in booth #1626 during the exhibit floor hours, which run from Monday, June 6 through Wednesday, June 8 from 10:00 a.m. to 6:00 p.m.

Again this year, our CEO Adnan Hamid is participating in the DAC technical program. He will be presenting in the “How Portable Stimulus Addresses Key Verification, Test Reuse, and Portability Challenges” session on Monday, June 6, from 1:30 p.m. to 5:00 p.m. This tutorial was organized by Accellera and the Portable Stimulus Working Group (PSWG), a standards effort we have discussed at length in previous posts, so you will hear the latest status directly from the experts.

We repeat our invitation to join us at DAC next week. Please attend the tutorial, stop by our booth, and  let us know if you’d like to schedule a particular time with Breker for a demonstration, discussion, or presentation in our suite. We look forward to seeing you in Austin!

Tom A.

The truth is out there … sometimes it’s in a blog.

Tags: Accellera, Agnisys, austin, Breker, cache coherency, cloud, dac, Design Automation Conference, EDA, functional verification, graph, graph-based, NoC, portable stimulus, PSWG, scenario model, Semifore, simulation, SoC verification, Synopsys, Trek, TrekSoC, uvm, Verdi, VIP

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